Apparatus and method for carrier state modulation

ABSTRACT

A carrier state modulator system is described in which a stream of digital data bits is encoded by modulating the amplitude or phase of a carrier wave. A transmitter directly modulates the amplitude or phase of a selected number of cycles of the carrier in accordance with the state of each digital data bit. This method of direct generation of an amplitude or phase modulated carrier wave differs from mixing a phase amplitude baseband modulation onto a higher carrier frequency.

This application claims priority to provisional application Ser. No.61/317,387 filed Mar. 25, 2010.

BACKGROUND

Wireless spectrum for RF data transmissions is scarce due to massivelyincreased demands. Therefore, methods that can improve spectralutilization are needed. Spectrum sharing and local reuse are two ways togain improvement, as well as signal design and detection technologyadvances. Digitized data is often transmitted using baseband tuning andfiltering at a receiver. Filter tuning rejects by attenuation most otherfrequencies that are outside of the channel passband. However, tuning byfiltering limits the data rate that can be transmitted in a band ofspectrum, as the baseband content cannot change rapidly because it isbeing averaged over time by the filter.

SUMMARY OF THE INVENTION

The carrier state modulator system of the present disclosure includes atransmitter for transmitting one or more bits of digital data. Thetransmitter includes an oscillator to generate a carrier frequencyhaving a voltage amplitude and a modulator to modulate the voltageamplitude on the basis of the one or more bits of digital data and tooutput a carrier state modulated signal. A transmitter transmits thecarrier state modulated signal, wherein the modulator modulates aspecified number cycles of the carrier frequency for each bit of the oneor more bits of digital data.

The carrier state modulator system of the present disclosure alsoincludes a receiver for demodulating digital data bits from a carrierstate modulated signal received from a transmitter. The receiverincludes an antenna to receive the carrier state modulated signal and astatistical detector to determine a phase score for a specified numberof cycles of the carrier state modulated signal based on a first numberof samples of an amplitude on a positive side of each cycle of thecarrier state modulated signal that is above a selected amplitude and asecond number of samples of an amplitude on a negative side of eachcycle of the carrier state modulated signal that is below the selectedamplitude. A controller can demodulate a value of a digital data bit ofthe carrier state modulated signal based on the phase score; and aninterface unit outputs the value of the digital data bit of the carrierstate modulated signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an embodiment of a transmitter of a carrierstate modulator in accordance with the present invention;

FIG. 2 is a block diagram of an embodiment of a receiver of a carrierstate modulator in accordance with the present invention;

FIG. 3 illustrates a carrier state modulated signal for 10 digital bitseach coded in 6 cycles of the carrier wave;

FIG. 4 illustrates a carrier state modulated signal for 6 digital bitseach coded in 10 cycles of the carrier wave;

FIG. 4 a illustrates a redundant carrier state modulated signal for the6 digital bits each coded in 10 cycles of the carrier wave of FIG. 4;

FIG. 5 illustrates a carrier state modulated signal for 6 digital bitseach coded in 10 cycles of the carrier wave wherein the 0 state is coded180 degrees-out of-phase;

FIG. 5 a illustrates a redundant carrier state modulated signal for 6digital bits each coded in 10 cycles of the carrier wave of FIG. 5;

FIG. 6 is illustrates a carrier state modulated signal for 12 bits eachcoded in 5 cycles being received along with 3 strong other transmittersand 14 other weaker transmitters and background noise sources; and

FIG. 6 a illustrates the carrier state modulation signal of FIG. 6 afterthe 3 strong transmitters have been removed using the computationalnotch filter in accordance with the present disclosure.

DETAILED DESCRIPTION

The present invention is an alternative to baseband tuning andfiltering. The spectrally narrow signal design of the present techniquesemploy a statistically based tuning apparatus and method for datadetection that can yield a higher data rate and a higher spectralefficiency than filter tuning, as measured in bits per second based uponthe baseband or carrier frequency (bps/Hz).

The present technique is referred to herein as Carrier State Modulation(CSM). A simplified overview of the technique is described withreference to the apparatus of the present invention diagramed in FIG. 1and FIG. 2. The CSM system includes a transmitter 100 and a receiver200. A simplified embodiment of transmitter 100 in accordance with thepresent invention can include a carrier oscillator 116 that generates acarrier signal at a frequency (f) of n Hz, where n is an integer.Typically, the carrier signal is sinusoidal but that is not alimitation. Digital data that is to be transmitted is input in a streamof digital bits 110.

Control logic 112 integrates the modulation for the carrier signal andthe stream of digital bits. Control logic 112 can include a centralprocessing unit (CPU), gate array logic, or similar programmable logicand a memory, and a modulation output interface to the analog transitioncircuit 114. Memory within 112 may be used to store the stream ofdigital bits from input interface 110. The logic or processor within 112applies a specified number of cycles of the carrier signal that will beused to code each bit of the digital bit stream. A modulator circuit 114modulates the specified number cycles of the carrier oscillator 116signal at a specified voltage level for each bit of the digital bitstream. The CSM signal is amplified in a power amplifier 118 andtransmitted by, for example, an antenna 120, although other transmissiontechniques are contemplated without detracting from the techniquesdescribed.

FIG. 2 illustrates a simplified embodiment of a receiver 200 inaccordance with the present invention. Receiver 200 can include anantenna 210 to receive the CSM signal. Note that antenna 210 alsoreceives transmissions from transmitters close to the frequency of theCSM signal but unrelated to the CSM signal. At least twoanalog-to-digital (A/D) converters 212 detect the amplitude at twopoints on the CSM signal. In an implementation, the A/D convertersdetect the CSM signal amplitude of a sinusoidal wave at about the peaksof π/2 radians (90°) and 3π/2 radians (270°). A/D converters 212 receiveinput from a synchronizing oscillator 214 aligned to the CSM transmitteroscillator. Accordingly, it may be appropriate, during initialization ofthe system, to use a computation on A/D samples within the logic andprocessor module 216 to synchronize the receiver oscillator to thetransmitter oscillator. Similarly, A/D converters 212 may besynchronized to receiver oscillator 214 for detecting the appropriatepeaks of the CSM signal and the bit coding boundaries of n cycles.

The amplitudes sampled by A/D converters 212 are provided to controllogic 216 for statistical and logical analysis. Control logic module 216can include a central processing unit (CPU), gate array logic, orsimilar programmable logic, a memory, a statistical analyzer, and anoutput interface 218 for the decoded bit stream. Control logic 216 cancount the detected amplitudes of the A/D converters that are at anexpected level as compared to the oscillator synchronization 214.Statistical analyzer within 216 can determine a number amplitudes above,or below, the expected level over the specified number of cycles anddetermine therefrom a digital level coded by the transmitter in the CSMsignal. The determined digital level of the bit is output through anyconvenient output device 218 such as digital readout, oscilloscope, ordevice that can store or operate upon the de-coded bit stream.

In an example, the frequency (f) of the carrier signal is 5 Ghz(gigahertz) and the specified number of cycles, n, for encoding eachdigital bit is 10 cycles. That is, 10 cycles of the carrier signal areused to transmit each digital bit. Presuming the digital data is binary,the data has only two states (e.g. 0 or 1) the rate at which data bitsare transmitted is 5 Ghz divided by 10 or (f/n), which is 500 Mbps(megabits per second). The transmitter modulates the carrier signal tocause the power amplifier to enhance the carrier signal for thespecified number of cycles to indicate a digital 1 state. Alternatively,the power amplifier could reduce the carrier signal for the specifiednumber of cycles to indicate a digital 0 state. Alternatively, the poweramplifier could both amplify for a 1 state and attenuate for a 0 state.It is noted that there could be more than two states, in which casevarious levels of and attenuation can be used. As such, the carriersignal amplitude is modulated with the bit states of the bit stream. Theresultant CSM signal is then transmitted.

The data coding states in Carrier State Modulation transmission are acarrier power level held for an integer n cycles. In a simple embodimentthere just two modulation states; a low power state codes a 0 bit and ahigher power state codes a 1 bit. For j repeated bits of the same value,the power level of the CSM signal is maintained for n Hz cycles. Forexample, the power level is held for 2n cycles for duplicated bits suchas 00 or 11 coding.

A slower transition between coding states implemented in analog circuit114 will tend to generate less interference in the form of low powerradiations in many frequencies. As n becomes larger, a transitionbetween states may take several cycles of the carrier signal to completeso as not to generate spurious power generation in other frequencies.The minimum n in the present invention is 1 cycle of the carrier signal.

When the carrier signal frequency is in, for example, the GHz frequencyrange, n could be quite large. The data rate is f/n bps, which is thecarrier frequency, f, divided by n cycles of the carrier signal bits persecond. That is, one bit in n cycles of the carrier transmissionfrequency. For example, a 4 GHz carrier with n=20 yields 200 Mbps for atwo-state digital signal. In a 4-state digital signal embodiment, thedata rate would be 2f/n, as each state codes one of each 2-bit sequence:00, 01, 10, and 11. Because the data is coded on the carrier directly,the present technique is a single frequency transmission that can occupya very narrow band, for example a 12.5 KHz license, even at GHzfrequencies with a sufficiently stable carrier oscillator 116. Thisfeature has the advantage of high spectral utilization in bps/Hz ascompared with traditional baseband and filtering transmission.

A method of the present disclosure is utilizes statistical computationaltuning. The A/D samples from converter 212 are composed of asuperposition of the entire RF receiving antenna 210; this compositeanalog signal contains the Carrier State Modulation transmissiontogether with the background noise and transmissions on nearbyfrequencies. Background noise is a superposition of random sources whichreinforce and cancel, resulting in an amplitude signal called the noisefloor. This same noise floor is present in a filter tuned passband also.

The receiver disclosed herein is designed to realize the benefits ofnarrow spectrum occupancy together with the f/n bps data rate. Filtertuning cannot be used as the carrier power states would be averaged totheir mid-amplitude value. Instead, the Carrier State Modulation signaland all nearby frequency transmissions are received and coexist in theantenna of the receiver, and a statistical method is employed to processout the Carrier State Modulation signal therefrom. Well-known methods ofdirectional antenna design, RF shielded housings, and physicalwaveguides may be used in combinations to reduce the unwanted othertransmissions and noise being received, prior to applying thestatistical digital tuning techniques disclosed herein.

The present technique requires at least two A/D) samples of the CSMsignal for each cycle of the carrier wave, but is often advantaged byhaving any larger even number of such samples in each cycle. Otherindependent transmissions in nearby frequencies that are received by theantenna have different amplitudes and phases that also cancel andreinforce randomly. These other independent transmissions are superposedand coexist with the CSM signal on the antenna and, as such, affect thedetected value in each A/D sample.

A statistical technique is used to detect the coded digital value of theCSM signal among the unwanted independent transmissions. A statisticaltuner detector within module 216 is briefly described in words in thissection, but is shown by graphical examples in FIGS. 3 through 6, andnumerically tabulated within the detailed description that follows. Thereceiver oscillator 214 can be synchronized with the carrier oscillatorin the control logic gate array 216 of the receiver. A secondsynchronizing computation within module 216 may be used to synchronizethe A/D converters 212 in the receiver. In an implementation,synchronization provides for the two A/D samples per cycle to be alignedat π/2 and 3π/2 radians of the carrier sine wave. That is, at thecarrier wave maximum amplitude.

Each digital bit is coded using n cycles of the carrier signal. In abinary bit a 1 state can be coded as a higher power level of the CSMsignal than the lower power 0 state over the n cycles of the carriersignal. The n state coding boundaries are located, for example, asdenoted in the FIG. 3, having a coding boundary every 6 cycles of thecarrier signal, and in FIG. 4, having a coding boundary every 10 cyclesof the carrier signal. In the lower power state the amplitude approacheszero but stays high enough to just maintain synchronization. The randomsuperposition of all the unwanted other transmissions received in theantenna has varying phase and amplitude that is always different in timeand is different from the Carrier State Modulation signal transmission.

Statistics of the A/D superposition across n cycles are tabulated,analyzed and monitored by the statistical detector A statistic hereinreferred to as phase score is used for detection of the Carrier StateModulation bit coded states. The present technique is data rate adaptiveso that n can be increased, or decreased, as necessary when thestatistics of the superposition have more, or less, variation. Further,the probability of a detection error can be reduced by selection of n,using the sampled statistics. The appropriate choice of n can allow forsuccessful transmission in nearly any RF congested location, at datarate f/n.

The details of the techniques disclosed are described with reference toFIG. 3, FIG. 4, FIG. 5 and FIG. 6. FIGS. 3-6 are the results ofsimulated experiments performed using computer modeling. These computermodeled experiments are referred to herein as experiments. The receivedamplitudes in antenna 210 decrease across these four experiments. Theseare 150, 100, 50 and 28 mV respectively. Received amplitudes decrease aslink spans (i.e., transmission distances) increase. Lower receivedamplitudes are affected by the background RF noise and by the relativestrengths of other independent transmissions in the receiving antenna.Four methods are presented to distinguish CSM signals amongst the othersin the receiving antenna. These are: (1) the choice of n, (2) the use ofredundancy, (3) the coding of the 0 bit with out-of-phase transmissionfor n carrier cycles, and (4) the subtraction of known strong othertransmissions in the receiving antenna. Each of the techniques isdescribed, herein below. It should be appreciated that any combinationof these 4 methods can used to optimize a CSM link for data rate anderror free detection with respect to the other independent transmissionsand random background RF noise in receiving antenna 210.

The phase score statistic for the statistical detection method of thepresent disclosure is defined as follows. In a receiver having two A/Dconverters, one at π/2 radians and one at 3π/2 radian, one count isrecorded when the first of two A/D samples has a positive value above DCat 0 mV and the count is incremented by one when the second A/D samplehas a negative value below DC at 0 on the same cycle of the CSM signal.The count is incremented for each cycle of the CSM signal within thecoding boundary. The expected value of the phase score for the otherindependent transmitters alone at random phase is n.

That is, the randomness of the other transmissions results in anexpected value for the count equal to the number of cycles in the codingboundary as the probability is 0.5 for the random composite to be eitherin the correct phase or not over the 2n A/D samples of an n cycle bitcoding cell. The minimum value for a phase score is 0 and the maximumvalue is 2n, when 2 A/D per CSM carrier cycle are used.

A threshold for demodulating a 1 bit coding and 0 bit coding from thephase score can be set based upon an initial calibration between thetransmitter and receiver of the CSM signal. An integer value for phasescore is used because the count resulting from the A/D converter valuesis an integer and thus avoids having a phase score with an indeterminatecoding. A nominal but often non integer value for a threshold is 1.5n,and the integer threshold may be selected near this nominal estimate.

FIG. 3 illustrates a CSM signal received by the receiver in a firstexperiment that included the Carrier State Modulation signal plus 13unwanted other transmissions in the antenna passband. The digital datacoded in the CSM signal in the transmitter was 1001001111. The raw A/Dsample data recorded from the receiving antenna is shown in Table 1 forthe first bit coded as a 1:

TABLE 1 Contribution Contribution Relative Amplitude Relative to firstA/D to second A/D frequency (mV) phase (mV) (mV 0.700 19.0 0.6 −18.520.00 0.734 43.5 0.3 −12.13 43.01 0.845 30.5 −0.9 −30.39 24.10 0.878 44.50.5 −18.81 34.10 0.902 33.5 −0.4 11.43 −21.31 0.936 22.0 0.2 15.66−12.01 1.000 150.0 0.0 150.00 −150.00 1.034 35.5 −0.1 33.28 −31.83 1.09726.5 −0.5 0.00 7.27 1.130 31.5 0.4 18.80 −26.52 1.165 37.0 −0.2 26.77−13.17 1.213 16.0 −0.6 −4.10 11.60 1.264 7.5 −0.3 3.58 1.19 1.300 11.50.7 2.75 −9.46

The sum of the superposition contributions to the first A/D is 178.37and could be reported as an integer of 178 mV. Notice that the unwantedother transmissions (those having a relative frequency other than 1.000)are randomly distributed about the CSM signal frequency and, as such,the amplitudes tend to cancel one another. Note also that the CSM signal(relative frequency 1.000) at 150 mV is the strongest received amplitudeand that it has relative phase 0.0 when the A/D is synchronized to theCSM signal. The contribution formula for each other transmission to thefirst A/D detected value can be calculated according to equation 1:

contribution=amplitude*sin[(phase+0.5)*π/frequency]  (1)

For example, in Table 1, the contribution for the carrier at 0.700relative frequency from the first A/D at π/2 is computed as:19*sin[(0.6+0.5)*π/0.7]=19*(−0.9749)=−18.52, as shown in Table 1.

Similarly, the contribution formula for each other transmission from thesecond A/D at 3π/2 can be calculated according to equation 2:

contribution=amplitude*sin[(phase+1.5)*π/frequency]  (2)

For example, in Table 1, the contribution for the carrier at 0.700relative frequency from the second A/D at 3π/2 is computed as:19*sin[(0.6+1.5)*π/0.7]=19*sin(3π)=0. These values are shown in Table 1.That is, each subsequent A/D increments by one π in formula 1.

In the experiment of FIG. 3, the receiver threshold for 1 bit and 0 bitdetection was set at 9.5. That is, when the phase score is 9 or lowerthe receiver decodes a 0 bit, and when the phase score is 10 or abovethe receiver decodes a 1 bit. When this range seems too narrow aroundthe threshold, n can be increased to increase range.

In the FIG. 3 example, the 12 A/D sample values for the first bit coded(as a 1) were 178, −143, 162, −187, 178, −148, 128, −133, 152, −167, 158and −119, resulting in a phase score of 12. This is because thesuperposition amplitude has the correct sign for a full power (i.e.,maximum modulating amplitude) 1 bit in all 12 of these A/D samples. The12 A/D samples for the second bit coded (as a 0) were −79, 95, −58, 6,3, 33, −50, 4, 62, −68, 7 and 38. Note that only 4 of these A/D sampleshave the correct sign for a full power 1 bit, resulting in a phase scoreof only 4. The 4 samples within this sequence of 12 samples with thecorrect sign for a Carrier State Modulation full power 1 coded bit are3, 62, −68 and 7. Since 4 is less than the 9.5 threshold, the receiverwould decode this second bit state as a 0 bit.

The coded 0 bit state by the transmitter was at an amplitude just highenough to maintain phase and synchronization, and the 1 bit coded stateamplitude was received at 150 mV in this experiment, although other 1bit encoding amplitudes can be used, as discussed herein below. Thecoded states span n=6 cycles in the FIG. 3 example, graphed as lightshade vertical grids, with a dark vertical grids at the coding stateboundaries.

FIG. 3 coded 10 bits in the sequence 1001001111. The phase scores forthese 10 coded bits in n=6 cycles were 12, 4, 3, 11, 8, 7, 12, 12, 12and 12, respectively. The expected value of the phase score is 6 for acoded 0 bit state. In this experiment, the four 0 coded bits had asample mean of 4+3+8+7=22 divided by 4, which is 5.50. The sample meanof the six 1 coded bit states was measured as(12+11+12+12+12+12)/6=11.83. The above 10 coded bits are shown at thebottom of FIG. 3 along with the above 10 phase scores.

FIG. 4 illustrates a CSM signal received by the receiver in a secondexperiment that included the Carrier State Modulation signal plus 11unwanted other transmissions in the antenna passband. Data bits arecoded in n=10 cycles of the carrier signal. There are 6 coded bit statesin FIG. 4. The coded states and their respective phase scores are shownbelow the received CSM signal in FIG. 4. The CSM signal was received atan amplitude of 100 mV for a 1 bit rather than the 150 mV in theexperiment of FIG. 3. In the experiment of FIG. 4, n was set larger at10, compared to 6 in the experiment of FIG. 3 to compensate for thelower received amplitude, which could make distinguishing a 1 bit from a0 bit on the receiver side more difficult. In both FIG. 3 and FIG. 4experiments, there are 2 A/D samples per cycle of the carrier wave,adjusted to be centered at π/2 and 3π/2. In other embodiments of thepresent invention, 4 or 6 A/D samples per cycle of the CSM signal can beprovided for in the hardware.

The digital data coded in the CSM signal was 101001. The raw datarecorded from the antenna is shown in Table 2 for the first bit coded asa 1:

TABLE 2 Contribution Relative Amplitude Relative to first A/D frequency(mV) phase (mV) 0.800 15 −0.6 −5.74 0.834 35 0.3 4.47 0.865 55 0.9−51.23 0.892 40 0.5 −14.85 0.902 45 −0.4 15.36 0.936 20 0.2 14.24 1.000100 0.0 100.00 1.026 60 0.7 −30.48 1.081 25 −0.5 0.00 1.125 15 0.4 8.821.161 20 −0.2 14.51 1.200 10 −0.6 −2.58

Similar to Table 1, the contribution formula for each other transmissionto the first A/D detected value can be calculated according toequation 1. The contribution to the second A/D detected value can becalculated according to equation 2 and is not shown in Table 2.

The sum of the contributions is 52.52, which is reported as integer 53.Note that if a 0 bit had been coded instead in these first n=10 cycles,the first A/D sample would have been 53-100=−47 and would have been ofthe wrong phase to score.

In the experiment of FIG. 4 there were coded 6 bits in the sequence101001. The phase scores of these 6 coded bits in n=10 cycles of thecarrier frequency boundaries were measured as 20, 13, 16, 5, 12 and 19,respectively. The expected value for the 0 bit state is 10, the value ofn, which is a result the randomness of the unwanted other transmissions,as discussed above in the experiment of FIG. 3. The sample mean of thecoded 0 bits was 13+5+12−30 divided by 3, which is 10. In thisexperiment, a threshold value for the phase score could be set at 15.5,so that a phase score of 15 or less would be decoded as a 0 bit and aphase score of 16 and above would be decoded as a 1 bit. The maximumphase score for a 1 bit is 20 in each coding boundary because the 1coded state can have a maximum of two readings above DC at zero fromeach of the two A/D converters on each of the 10 cycles in the codingboundary.

The third bit was coded as a 1 bit state and the phase score resulted ina value of 16, which is at the threshold borderline between a decoding a1 coded bit and 0 coded bit. An error could be made in decoding a bithaving a phase score on the threshold borderline. One approach tominimizing possible borderline decoding errors is to redundantly resendthe same sequence of bits and re-determine the phase scores. FIG. 4 agraphs an extension of the experiment of FIG. 4 for 6 more groups ofn=10 that redundantly code the same 101001 bit sequence. The phasescores for the redundantly transmitted sequence were 19, 7, 20, 15, 9and 16. This FIG. 4 a example illustrates the method (2) of the presentdisclosure, the use of redundancy.

In the present technique, the superposition A/D samples of the othertransmissions are independent random variables. When a CSM signal 1 bitis coded, this adds a systematic order on top of these random variables.Hence the phase scores depend upon the present superposition, whichalways differs.

In the redundant transmissions of FIG. 4 and FIG. 4 a, there was a phasescore of 20 and a 19, respectively, for the initial 1 coded bit. Thescores for the second 0 coded bit were 13 and 7, respectively. Usingredundancy, the receiver could detect these two 6 sequence bits by usingthe higher of two phase scores (20) for the coded 1 bit and the lower oftwo phase scores (7) for the coded 0 bit. This technique of selectingthe higher of the phase score measured for the coded 1 bit and the lowerof the phase score measured for the coded 0 bit was repeated for theremaining 4 coded bits of 1001. The resultant phase scores for the101001 transmitted bit sequence by the rule above now had phase scoresof 20, 7, 20, 5, 9 and 19, resulting in improved discrimination at theexpense of half the data rate. An alternative rule uses the sum of theredundant phase scores rather than the highest and lowest. For example,the 6 sums are 39, 20, 36, 20, 21 and 36. A new threshold of 30.5 can beused resulting in correct detection of each coded bit. Other rules arecontemplated.

The data rate using the redundancy is f/20 bps instead of 10 becausetwice as many cycles of the carrier signal are being used for each codedbit. However, the possibility of a decoding error is reduced as thephase scores of 20, 20 and 19 are more clearly above the 15.5 thresholdfor 1 bit coding and the phase scores of 7, 5 and 9 are more clearlybelow this 15.5 threshold for 0 bit coding as compared to thenon-redundant decoding of the experiment in FIG. 4. In this redundantFIG. 4 and FIG. 4 a example if the carrier was at 600 MHz, the data ratewould be 600/20=30 Mbps. If the allocated channel at 600 MHz was only 30KHz wide, then the spectral efficiency would be 1000 bps/Hz.

FIG. 5 and FIG. 5 a illustrate an experiment of the method (3) of thepresent disclosure, the out-of-phase transmission of the 0 coded bit.Here the bit coding and the other transmitters were the same as in theexperiment of FIG. 4 and FIG. 4 a. However, an amplitude of 50 mV,instead of 100 mV, was received, which can make distinguishing between acoded 1 bit and coded 0 bit in the resultant CSM signal received inantenna 210 more difficult. In the FIG. 5 example, a coded 0 bit istransmitted at full amplitude 180 degrees out-of-phase with the 1 bitcoding, rather than at an in-phase low amplitude as in the experiment ofFIG. 4. In an implementation, there are two synchronized oscillatorsrunning at the same frequency in the transmitter: a first oscillatorrunning 180 degrees out-of-phase with a second oscillator. In this case,a 1 coded bit is transmitted using the in phase oscillator and a 0 codedbit is transmitted using the out-of-phase oscillator. The analogtransition circuit 114 in transmitter 100 can effect this phasetransition smoothly, again so as to not generate interference productsin many other frequencies.

The bits coded and the phase scores are displayed at the bottom of FIG.5 and FIG. 5 a. The A/D samples are the same as in FIG. 4 and FIG. 4 a,except that the A/D sample are 50 mV lower in the positive direction and50 mV greater in the negative direction for all n=10 bit states in thisembodiment. Otherwise, only the coded 1 bit states would have seen the50 mV amplitude change (from 100 mV in FIG. 4 to the 50 mV of FIG. 5).That is, the coded 1 bit was received at the reduced 50 mV, whereas thecoded 0 bit was now received at −50 mV (i.e., 50 mV, 180 degreesout-of-phase).

Similar to the experiment of FIGS. 4 and 4 a, FIG. 5 a is a redundanttransmission of the bits of FIG. 5. The selected best discriminationphase scores from FIG. 5 and redundant FIG. Sa transmissions using thehighest/lowest rule, discussed above, was 15, 16 and 16 for the 1 codedbits, and 2, 1 and 7 for the 0 coded bits. The summation rule of addingthe redundant phase scores resulted in sums of 29, 13, 30, 10, 15 and 28for the 6 redundantly coded bits. With a threshold now set at 22.5, weagain make the correct bit detections with both alternative rules.

The coded 1 bit scores are lower than the phase scores of 20, 20 and 19of FIG. 4 due to the 50 mV lower received amplitude. However, the coded0 bit phase scores are lower than the phase scores of 7, 5 and 9 of FIG.4 due to the out-of-phase full power transmission of this alternativeembodiment, compared to the low power transmission in FIG. 4 for coded 0bits.

The first 20 A/D samples in the experiment of FIG. 4 coded as a 1 bitwere 53, −46, 50, −63, 82, −103, 120, −130, 128, −110, 79, −43, 14, −6,27, −76, 141, −203, 245 and −255 that resulted in a phase score of 20.That is, all of the 20 A/D measurements had the correct sign. The A/Dsample values for the second coded bit (as a 0) in FIG. 4 were 136,−101, 68, −51, 57, −80, 108, −127, 126, −105, 71, −31, −4, 30, −46, 54,−53, 42, −21 and −11. This second group has a phase score of 13, wherethe correct signs were in samples 136, −101, 68, −51, 57, −80, 108,−127, 126, −105, 71, −31 and −11. The A/D samples for the second 0 codedbit in FIG. 5 were 86, −51, 18, −1 . . . , which is the A/D sample valueadjusted for the amplitude voltage (50 mV in this experiment). Thesevalues were calculated as 86=136−50, −51=−101+50, 18=68−50 and −1=−51+50from the FIG. 4 A/D samples.

In some implementations of the disclosed technique, the receivedamplitude of the Carrier State Modulation signal could be lower than the150 mV, 100 mV and 50 mV used in the experiments of FIGS. 3-5. In such acase, it could be useful to use additional A/D converters to enhance thestatistical analysis. For example, three A/D converters could becentered at 4π/10, 5π/10 and 6π/10 radians for the positive portion ofthe wave of the Carrier State Modulation signal, and centered at 14π/10, 15 π/10 and 16 π/10 radians for the negative portion of wave ofthe CSM signal. In this example, the perfect phase score would be 6ncounts when coding a full power 1 bit, compared with the 2n counts whenusing 2 A/D samples per cycle as in FIG. 3, FIG. 4 and FIG. 5. In thiscase, the expected value of the phase score would be 3n when coding alow power 0 bit. That is, the number of A/D samples values times thenumber coding cycles.

It should also be appreciated that increasing n can help to recover thecoded bits when the Carrier State Modulation received signal amplitudeis low compared to the other transmissions in the receiving antenna.

The method (4) of the present disclosure is includes a computationalnotch filtering to subtract out known unwanted strong transmitters beingreceived in the receiver antenna. This method is described andillustrated in the experiment of FIG. 6 and FIG. 6 a. In thisexperiment, the receiving antenna received a superposition of 3 strongknown unwanted transmitter signals, a CSM signal at only 28 mV, and 14other noise sources and lower power transmitters (lower than 28 mV each,the highest of these being at 12, 11 and 9 mV). The 3 strongest unwantedtransmitter frequencies can be known from their licenses (each close-byto the CSM frequency) and their average amplitudes were measured with aspectrum analyzer instrument. The unwanted strongest transmitterfrequencies can also be found with a spectrum analyzer instrumentwhether they are licensed or unlicensed. What needs to be determined istheir phase relative to the CSM synchronizer oscillator 214. Theserelative phases are found by iteration within an embedded processor inmodule 216. As will be shown below, just close estimation of theserelative phases can be helpful. FIG. 6 a shows the result of subtractingout the 3 unwanted strongest transmitters. FIG. 6 codes 12 bits in n=5carrier cycles, all I's for simplicity of presentation. As in the othergraphical FIGS. 3-5, the bit coded and the phase score is displayed atthe bottom of FIG. 6 and FIG. 6 a.

The three unwanted strongest transmitters had the following relativefrequencies, amplitudes and relative phases. The first has a relativefrequency of 0.897625, received amplitude of 104 mV and relative phaseof 9.2. The second has frequency 0.97625, received amplitude 96 mV andrelative phase −7.5. The third strong transmitter has a relative offrequency 1.065375, received amplitude of 85 mV and relative phase of 3.

The phase scores in FIG. 6 are 7, 3, 9, 10, 7, 3, 3, 7, 0, 10, 10, 6.The expected value for a 0 coded bit is 5 (because n=5), and the maximumvalue for a 1 coded bit is 10 (because there are two A/D samples foreach of 5 cycles of the CSM signal). If the threshold were set at 7.5(only phase scores of 8, 9 or 10 would identify a 1 coded bit), then wewould have made 8 bit decoding errors out of the 12 coded bits in theFIG. 6 example. However, in FIG. 6 a after estimating the relativephases of the 3 strongest unwanted transmissions and subtracting theirindividual contributions out of each A/D using formula 1, the phasescores resulted in 11 of the 12 bits coded in the 1 state now being atthe maximum phase score of 10 and one at a phase score of 8, thusdetecting all twelve 1 coded bits correctly.

Because the 14 weaker sources at random should average towards 0 mV insuperposition, while the CSM signal always contributed 28 mV in absolutevalue. The phase converging process found average absolute residualvalues (the A/D minus the 3 strongest contributions) to be about 25 mVwhen the phase estimates got close to their actual relative phasevalues, and diverged to over 100 mV (near the average of the 3 strongestamplitudes when the phase estimates were not close to their actualvalues). For example, with the relative phases at 11, −5 and 5 theabsolute residual value was about 70 mV. Then with the relative phasesat 10, −6 and 4 the absolute residual value had decreased to about 41mV. But at relative phases 9.6, −7.1 and 3.4 (getting close to theiractual relative phase values) the residual was near its approximateminimum of 25 mV, and the phase scores were the same as shown in FIG. 6a. In actual implementation, the memory in receiver module 216 canbuffer A/D samples to match the delay time of the phase iterationcalculation, and then proceed in real time computing and subtractingeach unwanted contribution per equation 3 incremented by 1π.

contribution=amplitude*sin[(phase+−0.5)*π/frequency]  (3)

wherein amplitude is a level of the unwanted frequency, phase is thephase of the unwanted frequency relative to the A/D samples, i=1 for thefirst A/D sample and i is incremented by 1 for each additional A/Dsample, and frequency is the unwanted frequency relative to the carrierstate modulation signal.

A Carrier State Modulation signal transmission has an initializationprocess. This process starts by A/D sampling the antenna signal for aperiod of time, with that sampled signal being made up of whatever wasbeing received. Then a test sequence of different n Hz full powerCarrier State Modulation transmissions (coding a 1 bit) interspersedwith n cycles coding a 0 bit or other selected test sequence is codedand transmitted. The variation in decoding by the receiver is assessedin order to select a suitable n and a threshold for the detector rule.The receiver apparatus contains logic to closely center the A/D samplesto the full power 1 bit coding on the carrier. One method in logic forthis centering process is to select a preset time offset increment fromthe many included. Other alternative or equivalent means might beutilized to synchronize the A/D sampling. Centering could be judged tobe achieved when the phase scores cluster near their kn maximum for ksamples in n cycles.

Carrier State Modulation transmissions are rate adaptive, and can bechanged when more random variation appears or lessens, such as at nightand daytime RF traffic differences. That is, n and/or the transmissionmodulation amplitude value can be varied based on the number of unwantedsignals and levels received at the receiver antenna. Techniques havebeen described above to account for variations in the number and levelof unwanted signals: changing n, using redundancy, coding 0 bits without-of-phase transmission, and subtracting values of known receivedunwanted signals. It should be appreciated that small redundant blocksof bits could be transmitted more than 2 times when this is useful forimproved error performance, or simply when customer data is slackcompared to link capacity. It should further be appreciated that thehardware apparatus could be designed in a variety of logics, embedded orexternal processors and accompanying software that meet the requirementsof a Carrier State Modulation link.

Other embodiments of the invention are within the scope of the followingclaims.

1. A transmitter for transmitting one or more bits of digital data,comprising: an oscillator to generate a carrier frequency having avoltage amplitude; a voltage modulator to modulate the voltage amplitudeon the basis of the one or more bits of digital data and to output acarrier state modulated signal; and a transmitter to transmit thecarrier state modulated signal, wherein the voltage modulator modulatesa selected number of one or more cycles of the carrier frequency foreach bit of the one or more bits of digital data.
 2. The transmitter ofclaim 1, wherein a first level of digital data causes the modulator toincrease the carrier voltage amplitude to a level greater than for asecond level of digital data.
 3. The transmitter of claim 2, wherein thesecond level of digital data causes the voltage modulator to decreasethe carrier voltage amplitude.
 4. A transmitter for transmitting one ormore bits of digital data, comprising: a first oscillator to generate acarrier frequency having a voltage amplitude; a phase modulator tomodulate a phase of the carrier frequency on the basis of the one ormore bits of digital data and to output a carrier state modulatedsignal; and a transmitter to transmit the carrier state modulatedsignal, wherein the phase modulator modulates a selected number of oneor more cycles of the carrier frequency for each bit of the one or morebits of digital data, and wherein a first level of digital data causesthe phase modulator to output the carrier state modulated signal inphase with the carrier frequency and a second level of digital datacauses the phase modulator to output the carrier state modulated signal180 degrees out-of-phase with the carrier frequency.
 5. The transmitterof claim 4, comprising: a second oscillator to generate the carrierfrequency 180 degrees out-of-phase with the first oscillator, wherein,when the digital data is the first level then the phase modulatorselects the carrier frequency from the first oscillator and when thedigital data is the second level then the phase modulator selects thecarrier frequency from the second oscillator. 6.-13. (canceled)
 14. Amethod of coding one or more bits of digital data, comprising:modulating a voltage amplitude at a carrier frequency on the basis ofthe one or more bits of digital data; outputting a carrier statemodulated signal, wherein a selected number of one or more cycles of thecarrier frequency are modulated in the modulating step for each bit ofthe one or more bits of digital data.
 15. The method of coding of claim14, wherein a first level of digital data causes an increase in thevoltage amplitude to a level greater than for a second level of digitaldata.
 16. The method of coding of claim 15, wherein the second level ofdigital data causes a decrease in the voltage amplitude.
 17. A method ofcoding one or more bits of digital data, comprising: modulating a phaseof a carrier frequency on the basis of the one or more bits of digitaldata; outputting a carrier state modulated signal, wherein themodulating step includes modulating the phase of a selected number ofone or more cycles of the carrier frequency for each bit of the one ormore bits of digital data, and wherein a first level of digital datacauses outputting of the carrier state modulated signal in phase withthe carrier frequency and a second level of digital data causesoutputting of the carrier state modulated signal 180 degreesout-of-phase with the carrier frequency. 18-25. (canceled)